WHY SPLIT ONE CHIP INTO SEVERAL

Smaller dies, better yield

chiplets: several small dies, not one giant one

A yield model from earlier in this course shows that yield falls sharply as die area grows. Splitting one huge design into several smaller chiplets, each fabricated and tested separately, sidesteps that penalty, and lets each chiplet even use whichever process node suits it best.

Smaller dies yield better, and a bad chiplet is cheaper to lose than a bad giant die.

2.5D INTEGRATION

Chiplets, side by side on an interposer

In a 2.5D package, multiple chiplets sit side by side on a silicon interposer, a thin slice of silicon carrying dense wiring and through-silicon vias, or TSVs, that route signals vertically down to the package substrate below.

The interposer acts like an extra, very fine wiring layer built specifically to connect chiplets to each other.

THROUGH-SILICON VIAS

Wiring that runs straight through silicon

a vertical connection, drilled through the die

A through-silicon via is a hole etched completely through a piece of silicon and filled with metal, letting a signal pass straight through instead of only across the surface. TSVs are what make both silicon interposers and true 3D die-stacking possible.

A TSV turns silicon itself into wiring, not just a substrate for wiring.

2.5D VS. 3D

Side by side, or stacked directly

2.5D Chiplets sit side by side on a shared interposer

3D Chiplets stack directly on top of one another, connected by TSVs

2.5D's advantage Easier to build and test each chiplet independently

3D's advantage Shorter connections and a smaller overall footprint

Both are ways of making several dies behave electrically like one.

UNIT 42 STUDY COMPLETE

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Ready for the Fab Challenge?

You've covered interposers, TSVs, and why some chips are now built from several dies.