EVERYTHING SO FAR, IN ORDER

One flow, start to finish

wafer, FEOL, BEOL, test, dice

This unit is the whole course laid end to end. A finished chip starts as a bare wafer, passes through front-end and back-end fabrication, gets tested while still on the wafer, and finally gets diced into the individual chips a package will hold.

Nothing here is new: it's everything already covered, in the order it actually happens.

THE BUILD, IN ORDER

From bare wafer to tested die

Start A bare, polished silicon wafer

Front-end (FEOL) Wells, gate stack, implants, anneal, silicide

Back-end (BEOL) Contacts, then metal layer after metal layer, each with its vias

Passivation and pads A protective final layer, opened only where pads need to connect

Wafer test Every die is probed electrically before it ever leaves the wafer

Dicing The wafer is cut apart into individual chips, ready for packaging

Packaging picks up exactly where this flow leaves off.

A REAL NUMBER

Hundreds of steps, months of time

often 1,000+ process steps, months start to finish

A leading-edge logic chip can pass through well over a thousand individual process steps across its full flow, and take several months from a bare wafer to a finished, tested die. Every unit in this course is one small piece of that much longer sequence.

No single step is exotic; there are just an enormous number of them, done precisely, in order.

UNIT 30 STUDY COMPLETE

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Ready for the Fab Challenge?

You've covered the whole build, from bare wafer to a tested, diced chip, in order.