UNIT 12 • LAYERS IN ACTION

A clean surface before every layer

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SC-1

Ammonia, hydrogen peroxide, and water. Removes particles and organic residue

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SC-2

Hydrochloric acid, hydrogen peroxide, and water. Removes metal ions

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Piranha or plasma

Sulfuric acid and peroxide, or oxygen plasma, strip heavy organics and resist

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Dilute HF dip

Removes native oxide right before the next step

The RCA clean, developed at RCA in the 1960s, is still the backbone of wafer cleaning.

Fabs clean the wafer over and over, because a stray particle or metal ion can kill a die.

SHALLOW TRENCH ISOLATION

One isolation step uses four tools

1 · Pad oxide and nitride Grow a thin oxide, then deposit silicon nitride by LPCVD

2 · Etch the trench Pattern, then plasma-etch through the nitride and into the silicon

3 · Liner and fill Grow a thin liner oxide, then overfill the trench with CVD oxide

4 · Polish CMP flattens the oxide and stops on the nitride

5 · Strip the nitride Hot phosphoric acid removes it, leaving oxide-filled isolation

Growth, CVD, etch, and CMP team up to isolate neighboring transistors.

COPPER DAMASCENE

Cannot etch copper? Fill a trench instead

1 · Insulator Deposit the interlayer dielectric by CVD

2 · Etch Pattern and etch trenches, and via holes, into it

3 · Barrier and seed Sputter a Ta/TaN barrier, then a thin copper seed

4 · Plate Electroplate copper until it overfills the trenches

5 · Polish CMP removes the excess, leaving copper only in the trenches

Copper forms no volatile compounds that a plasma etch can pump away, so fabs etch the trench in the insulator and fill it instead.

Damascene turns 'copper cannot be etched' into 'fill the trench.'

MATCHING TOOL TO FILM

Which tool builds which layer

Gate and isolation oxide Furnace oxidation

Polysilicon and nitride LPCVD

Oxide between metal layers PECVD

Aluminum, Ti, Ta, copper seed Sputtering (PVD)

Copper wiring Electroplating

Tungsten plugs CVD

High-k gate dielectric ALD

The film, its thickness, and the temperature limit together pick the tool.

THERMAL BUDGET

Hot first, gentle last

furnace first, gentle last

Steps early in the flow can use furnace heat above 1,000 °C. Once metal wiring is on the wafer, later steps must stay below roughly 400 °C, or the copper and delicate insulators would be damaged. That is why a flow runs from hot to cool, and why PECVD exists.

Every step has to survive everything already built on the wafer.

HOW THIN?

A ladder of layer thicknesses

Isolation oxide Hundreds of nanometers

Polysilicon gate (classic) Roughly 100 to 200 nm

Copper wiring Tens to hundreds of nanometers

Barrier layer A few nanometers

High-k gate dielectric About 1 to 2 nm

Native oxide About 1 to 2 nm

Fabs control films from hundreds of nanometers down to a handful of atoms.

UNIT 12 STUDY COMPLETE

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Ready for the Fab Challenge?

You can walk through shallow trench isolation and copper damascene.