THE BIG PICTURE

From wafer to wired chip

Front end of line Builds the transistors themselves, in the top few hundred nanometers of silicon

Middle of line Adds the contacts that connect transistors to the first wiring layer

Back end of line Stacks a dozen or more metal wiring levels above

Scale Well over a thousand process steps, taking weeks to months for a single wafer

A transistor is the result of a long, ordered recipe, and each step prepares the next.

THE PROCESS FLOW

Layer by layer

Watch a transistor appear in eleven steps. Each one uses the same few building blocks you have met in the fabrication courses: deposition, lithography, etching, implantation and polishing.

Step through slowly: every layer exists because a later step needs it.

ALIGNMENT

Why the gate is self-aligned

If the source and drain were patterned with their own mask, any misalignment would leave one side overlapping the gate too much and the other side with a gap. The fix: build the gate first, then use the gate itself as the mask for the implant. The source and drain edges can then only land where the gate is, however far the lithography wanders.

Self-alignment is what makes billion-transistor chips possible.

THE TOOLS

Four kinds of machine

Lithography EUV light at 13.5 nm and multiple patterning print features far below the wavelength

Deposition and epitaxy Atomic layer deposition lays high-k films one atomic layer at a time; epitaxy grows SiGe and doped source/drain

Etch and polish Plasma etching cuts the patterns, and chemical-mechanical polishing flattens each level

Metrology Optical and electron-beam tools check dimensions of a few nanometers on every wafer

Every step is a tool you can also meet in the MEMS and Sand-to-Chip courses.

CHECK THE ORDER

Order the build

Isolation, wells, gate, source and drain, contacts, wiring.

UNIT 19 STUDY COMPLETE

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Ready for the Fab Challenge?

You've walked a transistor from a bare wafer to a wired device, and seen why the gate lines up the source and drain by itself.