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THE NEXT STEP

Wrap the fourth side

Gate-all-around The gate surrounds the channel on every side, so control is as good as geometry allows
Nanosheets Wide, thin ribbons of silicon, stacked and each surrounded by the gate
Nanowires The narrow version: less current per wire, but the best control
In production First shipped by Samsung in 2022; Intel and TSMC followed in the mid-2020s
A FinFET runs out of room to shrink. A stack of nanosheets does not, yet.

STACK THE SHEETS

Drive from stacking

Weff = N × 2(W + T)

Each sheet conducts around its full perimeter, so adding sheets multiplies the width without needing more footprint. And unlike fins, the width W of the sheet can be chosen freely: wide for fast logic, narrow for compact memory. The thickness T must stay thin, about 5 nm or less, to keep the gate in control.

Nanosheets bring back a free width knob that FinFETs had lost.

HOW IT IS MADE

Alternating layers, one etched away

Start Grow alternating thin layers of silicon and silicon-germanium on the wafer
Pattern Etch the stack into fins, as for a FinFET
Release Selectively etch away the SiGe layers, leaving the silicon sheets suspended
Wrap Deposit the high-k dielectric and metal gate into the gaps, around every sheet
The sheets exist only because one material can be etched away without touching the other.

THE NEXT TWISTS

Stacking the pair, powering from below

CFET Place the n-type device directly on top of the p-type one, halving the footprint of a logic cell
Backside power Run the power rails under the transistors, so the front can be used for signals only
Forksheet A wall between the n and p devices lets them sit closer together
Research frontier These are being developed for the late 2020s and beyond
Fold the pair, flip the power: more transistors in the same footprint.

CHECK THE ARCHITECTURES

Fin, nanosheet or CFET?

Fin, sheet, then stack: each step wraps the gate more and uses the footprint better.

UNIT 18 STUDY COMPLETE

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Ready for the Fab Challenge?

You've followed the transistor from fin to sheet to stacked pair, each step wrapping the gate further around the channel.