PlanarThe gate sits on top of a flat channel, and the deep silicon beneath is out of its reach
The leak pathBelow the surface, the drain can lower the barrier by itself (DIBL, Unit 26)
The ideaMake the channel a thin raised fin, and drape the gate over the top and both sides
TimingIntel introduced the FinFET, as Tri-gate, at 22 nm in 2011; foundries followed at 16/14 nm
If the gate cannot reach the channel's depths, make the channel thin.
DESIGN A FIN
Width from height
Weff = N × (2H + W)
A fin conducts along its two side walls and its top. Because the sides count, a tall fin adds a lot of channel width without adding footprint. The fin has to stay thin, around two-thirds of the gate length or less, so that the gate has influence all the way through it.
FinFETs buy width by going up, not out.
MORE SIDES, MORE CONTROL
Natural length
λ ≈ √(εSi ÷ εox · tSi · tox)
The natural length λ measures how far the drain's influence reaches into the channel. A short channel works well only when the gate length is a few times λ. Every extra side of gate shrinks λ, so a three-sided FinFET holds a shorter channel than a planar device, and a four-sided one does even better.
Short-channel control comes from geometry, not just from thin oxides.
THE FINE PRINT
What FinFETs cost
Quantized widthDrive current comes in whole fins: designers cannot ask for 1.6 fins
PatterningFins only a few nanometers wide at a tight pitch need spacer-based double or quadruple patterning, and later EUV
Self-heatingA narrow fin carries heat away poorly, so the device runs hotter than a planar one
ParasiticsA tall gate wraps more capacitance, and the source and drain contacts get cramped
FinFETs solved the leakage problem and created a patterning problem.
CHECK THE GEOMETRY
Planar or FinFET?
A raised fin gives more width per footprint and more of the channel under the gate.
UNIT 17 STUDY COMPLETE
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Ready for the Fab Challenge?
You've seen why the transistor stood up, and how many sides of gate it takes to hold a very short channel.