REMEMBERING A BIT

A memory hierarchy

Registers and caches Made of SRAM, fast enough to keep up with the processor core

Main memory Made of DRAM, many gigabytes, tens of nanoseconds away

Storage Flash, much larger and slower, and it keeps data with power off (next unit)

The trade Speed, density and cost pull in different directions, so computers use all three

Each memory is a different answer to "how do I make a transistor remember?"

SRAM

A latch of six transistors

Two cross-coupled inverters feed each other, so the cell has two stable states: Q high, QB low, or the reverse. Two access transistors, switched by the word line, connect the cell to the bit lines. SRAM is fast and needs no refresh, but six transistors per bit make it large.

SRAM holds a bit by feedback, as long as the power stays on.

DRAM

A leaky bucket

V(t) = V₀ · e^−t/τ

A DRAM cell is one access transistor and one capacitor. A charged capacitor is a 1, an empty one is a 0. The charge leaks away through the transistor and the junction, so every row has to be read and rewritten, refreshed, every tens of milliseconds. Leakage rises steeply with temperature, so hot chips refresh more often.

DRAM is the smallest cell, paid for with refresh.

THE COMPARISON

Fast and big, or small and leaky

Cell size SRAM is on the order of 100 F² or more; DRAM is about 6 F², where F is the minimum feature size

Speed SRAM answers in about a nanosecond; DRAM takes tens of nanoseconds

Refresh SRAM needs none; DRAM is refreshed continuously

Volatility Both forget their data when the power is switched off

Caches are SRAM because they must be fast. Main memory is DRAM because it must be cheap and big.

CHECK THE MEMORIES

SRAM or DRAM?

SRAM is fast and large, DRAM is dense and leaky.

UNIT 14 STUDY COMPLETE

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Ready for the Fab Challenge?

You've held, read and written both main memories, and seen why one is fast and large and the other dense and leaky.