PULL-UP AND PULL-DOWN

Two networks, one output

Pull-up network PMOS transistors between V_DD and the output

Pull-down network NMOS transistors between the output and ground

Duals Where one network has transistors in series, the other has them in parallel

Never both For every input, exactly one network conducts: the output is always driven

Every static CMOS gate is a pull-up network facing its dual pull-down network.

BUILD A GATE

Series is AND, parallel is OR

In a NAND gate the output goes low only when both NMOS are on, so they sit in series, and the PMOS in parallel. A NOR gate is the mirror image. Any logic function can be built from NAND gates alone, which is why NAND is called universal.

Flip the inputs and watch which network lights up.

WIRE THE NETWORKS

Series or parallel?

Series means AND, parallel means OR, and the two networks are duals.

WHERE THE POWER GOES

Dynamic plus static

P = α·C·V_DD²·f + V_DD·I_off

Each charge-up draws an energy C·V_DD² from the supply: half is stored on the load and half is lost as heat in the PMOS, and the discharge then turns the stored half into heat in the NMOS. So dynamic power scales with the square of the voltage and linearly with frequency and activity. Leakage adds a floor that does not depend on switching at all.

Voltage is the strongest lever: halve it and dynamic power falls to a quarter.

THE TRADE

Slower, cooler, or both

Lower V_DD Cuts dynamic power as V², but slows the gates, since the drive current falls

Lower activity Clock gating stops idle blocks from switching at all

Lower C Smaller transistors and shorter wires switch less capacitance

Dynamic voltage and frequency scaling Chips lower V_DD and f together when the workload is light

Every mobile processor is a continuous negotiation between speed and the battery.

UNIT 12 STUDY COMPLETE

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Ready for the Fab Challenge?

You've wired logic gates from transistors and tracked the two kinds of power that a CMOS chip burns.