A COMPLEMENTARY PAIR

One up, one down

PMOS to the supply Conducts when its gate is low, and pulls the output up to V_DD

NMOS to ground Conducts when its gate is high, and pulls the output down to 0 V

Shared gate The same input drives both gates, so exactly one is on

Complementary That is where CMOS gets its name: complementary metal-oxide-semiconductor

Input high gives output low, and input low gives output high. That is a NOT gate.

THE TRANSFER CURVE

Sweep the input

In the two steady states the output sits at a clean 1 or 0, and no current flows from supply to ground because one transistor is always off. Only while the input crosses the middle are both on, and then a brief surge of current flows. The steep part of the curve is where the gate has its gain.

CMOS only spends power when it switches.

RESTORING LOGIC

Noise gets cleaned at every gate

Because the curve is steep in the middle and flat at both ends, a slightly-too-high or slightly-too-low input is pushed to a clean 1 or 0 at the output. The room an input can wander before it is misread is the noise margin. A long chain of gates therefore passes bits without accumulating errors, which an analog signal path cannot do.

Digital logic is reliable because every gate re-draws the bit.

SIZING THE PAIR

Why the PMOS is wider

t_pd ≈ C·V_DD ÷ I_on

Hole mobility Holes are two to three times slower than electrons in silicon

Equal widths The PMOS pulls up more weakly than the NMOS pulls down, so rises are slower than falls

A wider PMOS Making W_p about 2 to 2.5 times W_n balances the two, and centres the switching point

Delay How fast the output swings is set by the load capacitance and the drive current

Drag the width ratio in the simulator and watch the switching point move.

CHECK THE IDEA

Why did CMOS win?

Almost no standby power, cleaned signals, and a balanced pair.

UNIT 11 STUDY COMPLETE

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Ready for the Fab Challenge?

You've built the basic CMOS cell, and seen why one transistor on, one off, is such a good idea.