THE NODES

Built at the leading edge

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Top AI chips are made on the most advanced processes available: NVIDIA's H100 and B200 on TSMC 4 nm-class processes, with newer chips moving to 3 nm and below. Smaller, denser transistors mean more MACs per mm² and less energy per operation.

Node names like '3 nm' are marketing labels now, not a measured feature size, but each new node still packs in more transistors.

THE FLOW

From bare wafer to AI die

An AI chip goes through the same steps you met in Sand to Chip, repeated for dozens of layers: deposit, pattern, etch, implant and polish, then build more than a dozen layers of copper wiring on top.

A leading-edge chip takes around three months and well over a thousand process steps.

EUV

Printing with 13.5 nm light

Extreme ultraviolet (EUV) lithography uses 13.5 nm light, made by hitting tiny tin droplets with a powerful laser tens of thousands of times a second. Because EUV is absorbed by almost everything, including air and glass, the scanner uses mirrors in a vacuum. ASML in the Netherlands is the only maker of EUV scanners.

ASML doesn't publish prices, but reports put a standard EUV scanner at around $180 million or more and a High-NA model at over €350 million.

THE TRANSISTOR

From FinFET to nanosheet

FinFET A thin fin of silicon wrapped by the gate on three sides; used from 22/16 nm down to 3 nm

Gate-all-around Stacked nanosheets fully wrapped by the gate: TSMC N2, Samsung 3 nm, Intel 18A

Backside power Power wires moved under the transistors to free space on top (Intel PowerVia, TSMC A16)

Better gate control means less leakage, which matters when a chip has hundreds of billions of transistors.

WHY IT MATTERS FOR AI

Every node is more AI per watt

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AI chips burn most of their power switching transistors and driving wires. A newer node lowers the energy of each switch and shortens wires, so more math fits within the same power limit. But each new node costs more per wafer, which pushes designers to use it only where it counts.

That cost pressure is one reason chips are split into chiplets on different nodes.

UNIT 9 STUDY COMPLETE

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Ready for the Fab Challenge?

You've followed an AI die through a leading-edge fab and seen why EUV lithography and new transistor shapes matter for AI.