THE BRIEF

Your mission

📝

Design an AI accelerator for serving a large language model. It must fit within the reticle limit per die, stay under a 1,000 W power budget, and have enough memory bandwidth to keep its math units busy.

Every choice in this course was a trade-off, and now you get to make them.

THE KNOBS

What you control

🎛️

Compute tiles More MAC units: more peak speed, more area and power

Precision FP16, FP8 or FP4: fewer bits, more operations per watt

HBM stacks More bandwidth and capacity, more cost and package area

Clock Faster clock: more speed but more power (and voltage)

Watch the readouts: area, power, peak speed and whether the chip is memory-bound.

BUILD IT

Design your accelerator

Adjust the design until it fits the area and power limits and its compute and memory are in balance.

A balanced chip is one where neither memory nor math sits idle.

LOOKING BACK

What you learned

🧭

🧠

The math

AI is matrix multiplication, so chips are built around MACs

🧱

The wall

Moving data costs more than the math; memory and packaging matter most

🔌

The cost

Power, cooling and supply chains limit how much AI the world can run

An AI chip is a whole system: math units, memory, package, power and software.

WHAT'S NEXT

Where to go from here

🚀

Explore how transistors work in the Transistors course, how chips are made in Sand to Chip, and how quantum chips compute differently in Quantum Computing Chips. The AI chip field changes every year, so check new chip announcements against what you've learned: compute, memory bandwidth, precision, power and packaging.

You now have the tools to read any AI chip spec sheet.

UNIT 21 STUDY COMPLETE

🏆

Ready for the Fab Challenge?

You've balanced compute, memory bandwidth, precision, power and area to design an AI chip of your own.