THE PACKAGE

More than a plastic case

For an AI chip, the package is where the system is built. The compute dies and HBM stacks must be connected by tens of thousands of wires only a few millimetres long. An ordinary circuit board can't make wires that fine, so they go on a silicon interposer: a slab of silicon with wiring but no transistors.

Advanced packaging puts memory close enough to act almost like it's on the chip.

CoWoS

Chip on Wafer on Substrate

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Chip The compute dies and HBM stacks

on Wafer ...are bonded with micro-bumps onto an interposer, still part of a wafer

on Substrate ...which is then mounted on an organic package substrate with larger solder bumps

TSMC's CoWoS has packaged most leading AI accelerators, from the P100 to the B200.

BUILD IT

Assemble an AI package

Put the steps of building a CoWoS package in order, from the bare interposer wafer to a finished, tested chip.

A single bad die can scrap the whole package, so every die is tested first.

THE VARIANTS

Bigger than a reticle

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The interposer can be larger than the reticle limit by stitching fields together. CoWoS-S uses one large silicon interposer; CoWoS-L, used for Blackwell, uses small silicon bridges embedded in a cheaper material; CoWoS-R uses fine organic wiring. Intel's EMIB and Foveros are similar ideas.

Packages several times the reticle size are now on the roadmap.

THE BOTTLENECK

Why packaging ran short

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When demand for AI chips jumped in 2023, CoWoS capacity, not wafer supply, became the main limit on how many could be shipped. TSMC has been expanding packaging capacity rapidly, and other companies, including Intel, Amkor and ASE, offer advanced packaging too.

Packaging went from an afterthought to one of the most valuable steps in making a chip.

UNIT 12 STUDY COMPLETE

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Ready for the Fab Challenge?

You've assembled an AI package from the dies up: interposer, micro-bumps, substrate and lid, and seen why packaging became a bottleneck.